The building blocks of conventional Complementary Metal-Oxide-Semiconductor (CMOS) logic technology consist of an N-channel MOS Field-Effect Transistor (NMOSFET) (1) and a P-channel MOS Field-Effect Transistor (PMOSFET) (11), as shown schematically in FIGS. 1(a) and 1(b), respectively. The examples shown use Semiconductor on Insulator (SOI) Technology, to facilitate comparison with the invention. The source (3,13) and drain (7,17) are n and p type, respectively, and the body (4,14) is p and n type, respectively.
As illustrated, and as will be readily understood by the man skilled in the art, these transistors (1,11) are normally “off”; in order to turn on either transistor (1,11) and allow current to flow between the source (3,13) and the drain (7,17), a sufficiently large gate voltage needs to be applied to the gate electrode (5,15) relative to the substrate (8,18) (the voltage applied to the substrate (8,18) is effectively the same as that applied to the source (9,19)). The minimum gate voltage (relative to the source) that is required to turn on a transistor is called the threshold voltage (Vt). Normally, Vt is positive for NMOSFET devices, and negative for PMOSFET devices.
FIG. 2 shows a logic inverter circuit (21), consisting of an NMOSFET (1) and a PMOSFET (11)—corresponding to those illustrated in FIGS. 1(a) and 1(b)—on a SOI wafer. To illustrate the operating principle, we shall assume that the threshold voltage (Vtn) for the NMOSFET (1) is 1.0 V, and that the threshold voltage (Vtp) for the PMOSFET (11) is −1.0 V, and the power supply voltage (VDD) is 3.0 V. We also define that the logic “1” state (or logic “high” state) corresponds to the voltage range of 2.0 to 3.0 V, and the logic “0” state (or logic “low” state) corresponds to the voltage of 0 to 1.0 V. When the input voltage (Vin) is 3.0 V (i.e., “high”) with respect to ground, the NMOSFET (1) is turned on (because the NMOSFET gate-to-source voltage is 3.0V, which exceeds Vtn), and the PMOSFET is off (because the PMOSFET gate-to-source voltage is 0 V). As a result, Vout is ˜0 V (i.e., “low”). On the other hand, when the input voltage is 0 V (i.e., “low”) with respect to ground, the NMOSFET is turned off (because the NMOSFET gate-to-source voltage is below Vtn), and the PMOSFET is turned on (because the PMOSFET gate-to-source voltage is −3.0 V, which exceeds Vtp). As a result, Vout is ˜3.0 V (i.e., “high”). Thus the inverter behaves as expected; a “high” input results in a “low” output and a “low” input results in a “high” output.
Note that a key feature of the CMOS inverter is that, in either state, the standby power consumption is very low because one of the transistors is always turned off; therefore there is very little current flowing between the power supply and ground. This is the main reason why CMOS technology overtook NMOS technology (which pre-dated CMOS) for digital applications in the 1980's.
The drive current of either the NMOSFET or the PMOSFET is approximately proportional to carrier mobility (electron or hole) and channel width. As illustrated in Table 1 (below), the mobility of electrons (μe) differs from the mobility of holes (μp) for a given semiconductor. Therefore in a CMOS inverter circuit, or a logic circuit based on CMOS inverters, because hole mobility is generally lower than electron mobility the channel width of the PMOSFET (Wp) is usually greater than that of the NMOSFET (Wn), to compensate. More specifically, the Wp/Wn ratio is set at the mobility ratio of μe/μp for the purpose of current matching.
For example, in Si-based logic circuits, the width of the PMOSFET is typically ˜2 times that of the NMOSFET, corresponding to the μe/μp ratio of Si (see Table 1), for current matching.
For a semiconductor that has very large μe/μp ratio (say a ratio of 20), one must engineer the device so as to make the Wp/Wn ratio similarly large for the CMOS inverter to achieve current matching. In such cases, the large Wp required for current matching results in large PMOSFET transistor sizes, in turn increasing the chip cost and making the overall circuit layout difficult to design. It should be noted that in many III-V semiconductors with high electron mobility, the hole mobility can be 20 times smaller.
Table 1 shows the electron and hole mobility for several different semiconductors, from which such large μe/μp ratios are apparent:
SiGeGaAsIn0.53Ga0.47AsInAsEg (eV)1.10.661.40.750.35μn (cm2/v-s)1,3503,9004,6007,80040,000μp (cm2/v-s)4801,900500350<500m*/mo0.1650.120.0670.0410.024
It is therefore an object of at least one embodiment of the present invention to obviate and mitigate the limitations of conventional CMOS devices.